FPGA Implementation for Optimized Adaptive Filter Based on Distributed Arithmetic

A novel pipelined architecture implementation of adaptive filter based on Distributed arithmetic (DA) for low­power, high­throughput, and low area. Filtering operations requires larger area and is not suited for higher order filters therefore causes reduction in the throughput. These problems have been overcome by efficient distributed formulation of Adaptive filters. Distributed arithmetic is an efficient procedure for computing inner products between a fixed and a variable data vector. Equivalen implementation of four­point inner product and weight increments unit to produce high throughput rate. Conditional signed carry­save accumulation is used in order to reduce the sampling period and area complexity for DA­basedinner­product computation. Power Is reduced by using fast bit clock for carry­save accumulation but a much slower clock for all other operations. To update the weights by using least mean square (LMS) adaptation and also minimize the mean square error between the estimated and desired output. It reduce the LUT’s, occupied slices, gate count for design.